SoC with RISC-V and Linux

1.      CPU core 1.1.  CPU core diagram Figure 1. The simple diagram of CPU core in the project Figure 2. CPU structure in Lab of Design of Digital Circuit (ETHZ) Figure 3. The structure diagram on Computer Organization and design RISC-V edition The first diagram is the simple representation of the CPU core in this project and the detail information will be exhibited in the following sections. The latter two figures are referenced when designing the CPU core in this project but these two design is much more different from the one in the project.  1.1. Implementation 1.1.1.      CoreTop.v Input/output name Input/output function CLK (input) The clock of the processor RESET (input) Reset the processor (all register goes to zaro) DATA [31:0] (output) Used for debug ADDRESS [31:0] (output) Used for debug 1.1.2.      InstructionMemory.v (It is used temporarily and will be...