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1.    CPU core
1.1. CPU core diagram
Figure 1. The simple diagram of CPU core in the project
Figure 2. CPU structure in Lab of Design of Digital Circuit (ETHZ)
Figure 3. The structure diagram on Computer Organization and design RISC-V edition
The first diagram is the simple representation of the CPU core in this project and the detail information will be exhibited in the following sections. The latter two figures are referenced when designing the CPU core in this project but these two design is much more different from the one in the project. 

1.1.Implementation
1.1.1.    CoreTop.v
Input/output name
Input/output function
CLK (input)
The clock of the processor
RESET (input)
Reset the processor (all register goes to zaro)
DATA [31:0] (output)
Used for debug
ADDRESS [31:0] (output)
Used for debug
1.1.2.    InstructionMemory.v(It is used temporarily and will be replaced by InstructionCache.v)
Input/output name
Input/output function
A [5:0] (input)
Address of instruction
RD [31:0] (output)
Instruction read from memory
1.1.3.    IF_ID_Register.v
Input/output name
Input/output function
PC [31:0] (input)
Program Counter
CLK (input)
The clock of the processor
RESET (input)
Register goes to zero
Instr [31:0] (input)
The instruction read from memory/cache
flush (input)
Used when the pipeline needs to stall
PC_o [31:0] (output)
Output of program counter
Instr_o [31:0] (output)
Output of instruction
1.1.4.    ControlUnit.v
Input/output name
Input/output function
OP [6:0] (input)
Opcode of instruction (Instruction[6:0])
Funct3 [2:0] (input)
Funct3 number of instruction
Funct7 [6:0] (input)
Fucnt7 number of instruction
EX_control [20:0] (output)
Use to control execution stage
MEM_control [6:0] (output)
Use to control Memory operand fetch
WB_control [3:0] (output)
Use to control Write Back stage
1.1.5.    RegisterFile.v
Input/output name
Input/output function
A1 [4:0] (input)
Register number in rs1
A2 [4:0] (input)
Register number in rs2
A3 [4:0] (input)
Register number needed to write back
WD [31:0] (input)
Write Data
RegWrite (input)
Write Enable
CLK (input)
The clock of the processor
RESET (input)
Register goes to zero
RD1 [31:0] (output)
Data in rs1
RD2 [31:0] (output)
Data in rs2
1.1.6.    ID_EX_Register.v
Input/output name
Input/output function
CLK (input)
The clock of the processor
RESET (input)
Register goes to zero
Enable (input)
Write Enable (pipeline stall)
flush (input)
Register goes to zero (branch target hit)
SrcA_i [31:0] (input)
Data in rs1 input
SrcB_i [31:0] (input)
Data in rs2 input
EX_control_i [20:0] (input)
Execution control input
MEM_control_i [6:0] (input)
Memory control input
WB_control_i [3:0] (input)
Write Back control input
U_type_immediate_i [31:0] (input)
U-type instruction immediate value input
J_type_immediate_i [31:0] (input)
J-type instruction immediate value input
I_type_immediate_i [31:0] (input)
I-type instruction immediate value input
B_type_immediate_i [31:0] (input)
B-type instruction immediate value input
S_type_immediate_i [31:0] (input)
S-type instruction immediate value input
RegDst_i [4:0] (input)
Register destination (rd) input
PC_i [31:0] (input)
Program counter input
ALUSrcB_S_type_i (input)
Control SrcB if the instruction type is S-type
RegisterRs1_i [4:0] (input)
Register rs1 (use for forwarding)
RegisterRs2_i [4:0] (input)
Register rs2 (use for forwarding)
EX_control [20:0] (output)
Execution control output
MEM_control [6:0] (output)
Memory control output
WB_control [3:0] (output)
Write Back control output
U_type_immediate [31:0] (output)
U-type instruction immediate value output

J_type_immediate [31:0] (output)
J-type instruction immediate value output
I_type_immediate [31:0] (output)
I-type instruction immediate value output
RegDst [4:0] (output)
Register destination (rd) output
PC [31:0] (output)
Program counter input
SrcA [31:0] (output)
Data in rs1 input
SrcB [31:0] (output)
Data in rs2 input
B_type_immediate [31:0] (output)
B-type instruction immediate value input
S_type_immediate [31:0] (output)
S-type instruction immediate value input
RegisterRs1 [4:0] (output)
Register rs1 (use for forwarding)
RegisterRs2 [4:0] (output)
Register rs2 (use for forwarding)
ALUSrcB_S_type (output)
Control SrcB if the instruction type is S-type
1.1.1.    ALUControl.v
Input/output name
Input/output function
Aluop [6:0]
Opcode of instruction (Instruction[6:0])
Funct3 [2:0]
Funct3 number of instruction
Funct7 [6:0]
Fucnt7 number of instruction
ControlResult [10:0]
Alu control logic
1.1.2.    ALU.v
Input/output name
Input/output function
a [31:0] (input)
Input 1
b [31:0] (input)
Input 2
aluop [10:0] (input)
ALU control logic 
result [31:0] (output)
Calculation result
branchCmp (output)
Branch comparison result
zero_division (output)
Divide zero
overflow_signed_div (output)
Division overflow
1.1.3.    EX_MEM_Register.v
Input/output name
Input/output function
CLK (input)
The clock of the processor
RESET (input)
Register goes to zero
MEM_control_i [6:0] (input)
Memory control input
WB_control_i [3:0] (input)
Write Back control input
ALUResult_i [31:0] (input)
ALU calculation result
StoreData_i [31:0] (input)
Data needed to be stored in memory (s-type instruction)
branchCmp (input)
Branch comparison result
zero_division (input)
Divide zero
overflow_signed_div (input)
Division overflow
RegDst_i [4:0] (input)
Register destination (rd) input
PC_i [31:0] (input)
Program counter input
BranchTargetAddress_i [31:0] (input)
Branch Target Address
WB_control [3:0] (output)
Write Back control output
ALUResult [31:0] (output)
ALU calculation result
StoreData [31:0] (output)
Data needed to be stored in memory (s-type instruction)
branchCmp (output)
Branch comparison result
zero_division (output)
Divide zero
overflow_signed_div (output)
Division overflow
RegDst [4:0] (output)
Register destination (rd) output
PC [31:0] (output)
Program counter output
MEM_control [6:0] (output)
Memory control output
BranchTargetAddress [31:0] (output)
Branch Target Address
1.1.4.     DataMemory.v(It is used temporarily and will be replaced by DataCache.v)
Input/output name
Input/output function
CLK (input)
The clock of the processor
A
Address of reading memory
WE
Write Enable
WD
Write Data
RD
Read Data
1.1.5.     MEM_WB_Register.v
Input/output name
Input/output function
CLK (input)
The clock of the processor
RESET (input)
Register goes to zero
WB_control_i [3:0] (input)
Write Back control input
ReadData_i [31:0] (input)
Data read from memory
ALUResult_i [31:0] (input)
ALU calculation result
PC_i [31:0] (input)
Program Counter of current instruction
WB_control [3:0] (output)
Write Back Control logic
RegDst [4:0] (output)
Register Destination
ReadData [31:0] (output)
Data read from memory output
ALUResult [31:0] (output)
ALU calculation result output
PC [31:0] (output)
Program Counter of current instruction output
RegDst_i [4:0] (input)
Register Destination output
1.1.6.     HazardUnit.v
Input/output name
Input/output function
RegSrcA_ID_EX [4:0] (input)
Register rs1 in execution stage
RegSrcB_ID_EX [4:0] (input)
Register rs2 in execution stage
RegDst_EX_MEM [4:0] (input)
Register Destination in memory operation stage
RegDst_MEM_WB (input)
Register Destination in write back stage
RegWrite_EX_MEM (input)
Register Write control in memory operation stage
RegWrite_MEM_WB (input)
Register Write control in write back stage 
ALUSrcA (input)
ALU Source A control logic
ALUSrcB [1:0] (input)
ALU Source B control logic
MemRead (input)
Determine whether the instruction in memory operation stage needs to read memory
RegDst_ID_EX [4:0] (input)
Register Destination in execution stage
RegSrcA_IF_ID [4:0] (input)
Register rs1 in decode stage
RegSrcB_IF_ID [4:0] (input)
Register rs2 in decode stage
ForwardA [1:0] (output)
Determine whether ALU Source A needs data forwarding
ForwardB [1:0] (output)
Determine whether ALU Source B needs data forwarding
WriteEnable_IF_ID (output)
Control the Write Enable of IF/ID register
ControlLogicStall (output)
Make control logic input zero
PCWriteEnable (output)
Control the PC to be next PC value or to stall

1.2. Brief introduction about each verilog file
1.2.1.    CoreTop.v
This top file includes all the connection between each components in the 5 stage pipeline processor. In the instruction fetch stage, Instruction memory/cache will return the value whose address is program counter in one or more cycles and then push them into the IF/ID register. Then the instruction will come into the next stage, decode stage. In this stage, the instruction will separate the instruction into different parts according to the RISC-V specification and also push them into ID/EX register. Next, if the instruction needs to do some calculation, it will be finished in the execution stage. It will also be pushed into EX/MEM register for memory operation stage. Finally, Write Back stage will happen if it is necessary.
1.2.2.    InstructionMemory.v
This file is the temporary memory for instruction cache. It only uses register in FPGA to store instruction.
1.2.3.    IF_ID_Register.v
This file includes all the information the decode stage needs and it will store new information on rising edge of the clock.
1.2.4.    ControlUnit.v
This file provides control logic based on the instruction and it will be transmitted every cycle until the instruction is completed.
1.2.5.    RegisterFile.v
This file includes 32 registers to store information and it supports synchronous read and write operation at the same rising edge of cycle.
1.2.6.    ID_EX_Register.v
This file includes all the information the execution stage needs and it will store new information on rising edge of the clock.
1.2.7.    ALUControl.v
This file will further deal with the information constructed by control unit and help the ALU generate the current calculation result.
1.2.8.    EX_MEM_Register.v
This file includes all the information the memory operation stage needs and it will store new information on rising edge of the clock.
1.2.9.    DataMemory.v
This file is the temporary memory for data cache. It only uses register in FPGA to store instruction.
1.2.10.MEM_WB_Register.v
This file includes all the information the write back stage needs and it will store new information on rising edge of the clock.
1.2.11.HazardUnit.v
Hazard Unit deal with the control and data dependencies in the pipeline. If the instruction in decode stage needs register values that will be written by the instruction in memory operation stage or write back stage, the value in the latter two stages can be forwarded to the former instruction so that the pipeline doesn’t need to be stalled. If the instruction after load instruction read register value that is the same as the destination register of load instruction, it should be stalled until the load instruction comes into write back stage. 

2.   System on chip
2.1. Cache System
2.1.1.    Cache System diagram
1.1.1.    Implementation
Input/output name
Input/output function
w_valid_d (input)
CPU request write data into memory
r_valid_d (input)
CPU request read data from memory
w_data_d [31:0] (input)
The data that needed to be written
CLK (input)
The Cache Clock (three times as Processor clk)
r_addr_i [31:0] (input)
The address of which CPU wants to read instruction
FIFO_empty_i (input)
The empty port of FIFO between CPU and instruction cache
addr_d [31:0] (input)
The address of which CPU wants to read or write data
FIFO_empty_d (input)
The empty port of FIFO between CPU and data cache
reset (input) (input)
Reset cache
r_valid_i (input)
CPU request read instruction from memory
rsp_d [1:0] (output)
Response to CPU from data cache
r_data_d [31:0] (output)
Data read from memory
rsp_valid_d (output)
Response valid port from data cache
r_data_i [31:0] (output)
Instruction read from memory
r_rsp_i [1:0] (output)
Response to CPU from instruction cache
rsp_valid_i (output)
Response valid port from instruction cache
DDR2 (output)
DDR2 port connection to physical memory
1.1.2.    Brief introduction of the function of cache system
To begin with, CPU will put its request on the asynchronous FIFO between cache and CPU so that cache will fetch it in the next cycle of cache. Next, cache includes three stage pipeline that are read from cache, comparison, and response. In the reading stage, it will read the set based on 2 to 11 bits and then push them into the register. Then the comparison logic will compare the tag, the first 20 bits of address. If the tag is the same, it means cache hit and it will do write or read operation in the final stage. Otherwise, cache will request SenderSolver to further deal with address. Moreover, cache use least recently used (LRU) policy to replace the block that is not needed and write back policy to write dirty block into memory. After that, SenderSolver will encapsulate information necessary to read or write memory and send it to the AXI master. AXI master is responsible for sending the address and receive data from memory through AXI4 bus. Instruction cache and Data cache will use AXI4 interconnect to communicate with AXI4 slave interface of Memory Interface Generator. Furthermore, the result will be sent by AXI4 bus and then dealt with by SendSolver to write back into the cache. The cache will send messages to ask the CPU send request again and finally, CPU will get the correct result.  
1.1.3.    Memory Interface Generator Settings
















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Week 1

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1. Linux Install the running environment (including riscv32-unknown-elf-gcc and qemu-system-riscv32). riscv32-unknown-elf-gcc is the cross compile, which can compile the operating system source code so that it can be used in 32 bit RISC-V. Qemu-system-riscv32 can simulate the 32 bit RISC-V environment on Ubuntu. Therefore, we can test the correctness of operating system without a completed CPU.  After finishing the installation, write a simple C program to test the correctness. Firstly, use the riscv32-unknown-elf-gcc to compile the source code and generate an executable file. Then, use qemu-system-riscv32 to run this executable file. This process is shown in following figure. 2. Bootloader Read the book called <Computer Organization and Design RISC-V Edition: The Hardware Software Interface>. This is a thick book for me to read it because I lack knowledge of computer systems. I particularly focused on the second part <Instruction: Language...
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Week 2

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1. Linux Implement several shell commands, such as sleep , pingpong , primes , find and xargs . 1. sleep can pause the operating system for a given time. (eg. sleep 100: the system will pause for 10 second) 2. pingpong can transmit a byte message between two processors via a pair of pipes, parent_pipe and child_pipe , one for each direction (in and out). The parent process will write message to parent_pipe[1] and the child receive this message from parent_pipe[0] . Then child responds with writing a message to child_pipe[1] and parent can read from child_pipe[0]. 3. primes is based on the idea Unix Pipes .  The first process feeds the numbers 2 through 35 into the pipeline. For each prime number, you will arrange to create one process that reads from its left neighbor over a pipe and writes to its right neighbor over another pipe. All the numbers can be divided by the prime number will be discarded as shown in the following figure.  Figure 1: the function of...
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Week 4

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1. Linux Implement lazy allocation, which will only allocate resource until it is actually needed. That is, sbrk function doesn't allocate physical memory, but just remembers which addresses are allocated. When the process first tries to use any given page of memory, the CPU generates a page fault, which the kernel handles by allocating physical memory, zeroing it, and mapping it. 2. Bootloader It was found that the u-boot transplantation tutorial on the Internet was performed on the Samsung template, which is different from the source code used by risc-v. 3. SoC Discuss how the operating system communicate with the CPU (system call) Search information to solve the problem of DDR2 SDRAM, which cause the whole project not to meet the expectation progress. Replace on chip DDR2 RAM with LUT RAM and Block RAM Can not support the compile file of operating system. Therefore, memory support is necessary
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