Week 6

1. Linux

Compile xv6. Since the CPU is 32 bit, the source code must be modified (mainly change pointer's increasing step length). Set the compile tool and simulating tool in Makefile to riscv32-unknown-elf-gcc and qemu-system-riscv32.

2. Bootloader

Booting the U-boot to the memory so that it can read the kernel from USB. 
Participate in designing and editing posters.

3. SoC

1. Construct Cache System (commits on Mar 2, 2020)
   1. Instruction cache: Single Port Distributed RAM (Xilinx Parameterized Macro)
   2. Data cache Single Port Block RAM (Xilinx Parameterized Macro)
2. Construct communication between cache system and memory by AXI4 full bus (commits on Mar 3, 2020)
   1. Reference document: UG586 MIG 4.2 User Guide, Note 5 of ECE-495/595 in ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
   2. Tools: Vivado Block Design
   3. IP core: Xilinx Memory Interface Generator, Xilinx AXI4 peripheral, Xilinx AXI4 interconnect
3. Construct communication between cache and cpu core (commits on Mar 3, 2020)
   1. Asynchronous FIFO (Xilinx Parameterized Macro)
4. Try to integrate operating system into the SoC
   1. Problem: No GPIO, No USB, Cache system have unknown bugs, boot can not correctly load the system

Further improvement

1. System on Chip
   1. General-purpose input/output (GPIO) to AXI4 interface (memory)
   2. USB driver to AXI4 interface (memory)
   3. PS/2 and VGA driver to AXI4 interface (memory)
   4. Complete verification of all the components
2. CPU Core
   1. Reorder buffer and Out of order execution
   2. Dynamic branch prediction
      1. Reference document: S. McFarling, "Combining Branch Predictors" DEC WRL Technical Report" 1993
   3. Superscalar processor

Notice: Other simulation figures will not be shown and it all exists on the github repository; thus, if user want to see the simulation figure, it can directly run behavioral simulation in Vivado with files in “tb” file folder.